Allwinner /D1H /SMHC[0] /SMHC_NTSR

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Interpret as SMHC_NTSR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (disable)HS400_NEW_SAMPLE_EN 0 (O90)CMD_SAMPLE_TIMING_PHASE 0 (O90)DAT_SAMPLE_TIMING_PHASE 0 (Disabled)CMD_SEND_RX_PHASE_CLR 0 (Disabled)DAT_RECV_RX_PHASE_CLR 0 (Disabled)DAT_TRANS_RX_PHASE_CLR 0 (Disabled)DAT_CRC_STATUS_RX_PHASE_CLR 0 (Disabled)CMD_DAT_RX_PHASE_CLR 0 (old_mode)MODE_SELECT

DAT_CRC_STATUS_RX_PHASE_CLR=Disabled, DAT_RECV_RX_PHASE_CLR=Disabled, DAT_SAMPLE_TIMING_PHASE=O90, CMD_DAT_RX_PHASE_CLR=Disabled, CMD_SEND_RX_PHASE_CLR=Disabled, CMD_SAMPLE_TIMING_PHASE=O90, DAT_TRANS_RX_PHASE_CLR=Disabled, MODE_SELECT=old_mode, HS400_NEW_SAMPLE_EN=disable

Description

SD New Timing Set Register

Fields

HS400_NEW_SAMPLE_EN

0 (disable): Disable hs400 new sample method

1 (enable): Enable hs400 new sample method

CMD_SAMPLE_TIMING_PHASE

0 (O90): Sample timing phase offset 90

1 (O180): Sample timing phase offset 180

2 (O270): Sample timing phase offset 270

3 (O0): Ignore

DAT_SAMPLE_TIMING_PHASE

0 (O90): Sample timing phase offset 90

1 (O180): Sample timing phase offset 180

2 (O270): Sample timing phase offset 270

3 (O0): Sample timing phase offset 0 (only for SD2 hs400 mode)

CMD_SEND_RX_PHASE_CLR

Clear command rx phase before sending the command

0 (Disabled): Disabled

1 (Enabled): Enabled

DAT_RECV_RX_PHASE_CLR

Clear the input phase of data lines before receiving the data

0 (Disabled): Disabled

1 (Enabled): Enabled

DAT_TRANS_RX_PHASE_CLR

Clear the input phase of data lines before transferring the data

0 (Disabled): Disabled

1 (Enabled): Enabled

DAT_CRC_STATUS_RX_PHASE_CLR

Clear the input phase of data lines before receiving the CRC status

0 (Disabled): Disabled

1 (Enabled): Enabled

CMD_DAT_RX_PHASE_CLR

Clear the input phase of command lines and data lines during the update clock operation

0 (Disabled): Disabled

1 (Enabled): Enabled

MODE_SELECT

0 (old_mode): Old mode of Sample/Output Timing

1 (new_mode): New mode of Sample/Output Timing

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